How Genode came to RISC-V Mar 22, 2016
Our new article provides a look behind the scenes of porting Genode to the RISC-V hardware architecture.
The experience report How Genode came to RISC-V complements our recent announcement about Genode's added RISC-V support with in-depth technical information. It briefly introduces the parts of the instruction set architecture (ISA) that were most relevant for the porting work, presents various challenges we encountered, and explains how we overcame them.
The article is written with two target audiences in mind: People interested in practical experiences with RISC-V, and developers who aspire to port Genode to new CPU architectures. Read the article...